library ieee;
use ieee.std_logic_1164.all;

entity nada is

Port(
	clk	: in std_logic;
	data_in : in std_logic_vector(39 downto 0);
	data_out : out std_logic_vector(39 downto 0)
);

end nada;



architecture Behavioral of nada is

	
begin
	data_out <= data_in;


end Behavioral;